Phase adjustment circuit for clock and data recovery circuit
US9294260B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Dec 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03598
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.