Register management in an extended processor architecture
US9298460B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2011 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Sep 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for enhancing the throughput of a processor by minimizing the number of transfers of data associated with data transfer between a register file and a memory stack. The register file used by a processor running an application is partitioned into a number of blocks. A subset of the blocks of the register file is defined in an application binary interface enabling the subset to be pre-allocated and exposed to the application binary interface. Optionally, blocks other than the subset are not exposed to the application binary interface so that the data relating to application function switch or a context switch is not transferred between the unexposed blocks and a memory stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.