Data synchronization circuit
US9298666B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2011 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Sep 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention concerns a circuit comprising: a first circuit block (302) adapted to receive a first clock signal (CLK1) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block (304) adapted to receive a second clock signal (CLK2) and to provide a second output data signal at a time determined by said second clock signal; a clock bus (314) coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit (312) coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.