Debugging an optimized design implemented in a device with a pre-optimized design simulation
US9298865B1 · kind B1 · utility
18Cited by
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22Claims
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Key dates
| Filing date | Mar 20, 2014 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Mar 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and mechanisms debug a device implementing an optimized design using a pre-optimized design simulation. For example, data indicating interconnect in a pre-optimized design to simulate may be received. A node in common between the pre-optimized design and an optimized design may be identified. A tap at the output of the node in the optimized design may be inserted for providing data for the simulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.