Semiconductor memory devices
US9299392B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2013 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Apr 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory devices include unit cells two-dimensionally arranged along rows and columns in one cell array block. The unit cells are classified into a plurality of cell subgroups, and each of the cell subgroups includes the unit cells constituting a plurality of the rows. Each of the unit cells includes a selection element and a data storage part. A word line is connected to gate electrodes of selection elements of the unit cells constituting each column. Bit lines are connected to data storage parts of the unit cells constituting the rows. A source line, parallel to the bit line, is electrically connected to source terminals of the selection elements of the unit cells in each cell subgroup. The source line is parallel to the bit line. A distance between the source line and the select bit line is equal to a distance between the bit lines adjacent to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.