Methods and apparatus for performing boosted bit line precharge

US9299404B1 · kind B1 · utility

Inventors

• Chin-Ghee Ch'ng · Air Itam, MY
• Wei Yee Koay · Kampung Bukit Kechil, MY
• Eu Geen Chew · Bayan Lepas, MY

Key dates

• Filing date: Mar 12, 2013
• Grant date: Mar 29, 2016
• Expiry date: Oct 29, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/419
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Integrated circuits with memory cells are provided. The memory cells may be arranged in rows and columns. Each column of memory cells may be coupled to a respective pair of data lines. The data lines may be precharged using precharge circuitry. The precharge circuitry may include n-channel precharge transistors, an equalizer transistor, an isolation transistor, a pull-down transistor, a voltage booster, and control logic. The voltage booster may provide boosted voltage signal for overdriving the n-channel transistors by pulsing a control signal. During first pulse of the control signal, the data lines may be charged up to an intermediate voltage level. During second pulse of the control signal, the data lines may be charged up to a positive power supply voltage level that is greater than the intermediate voltage level. Performing double boosted data line precharge in this way can help reduce leakage and improve memory performance.