Write operations in spin transfer torque memory
US9299412B2 · kind B2 · utility
51Cited by
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25Claims
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Key dates
| Filing date | Feb 26, 2014 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Feb 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a controller comprises logic to identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state, mask write operations to the second plurality of cells in the row, set the first plurality of cells to a parallel state, mask write operations to the first plurality of cells in the row, and set the second plurality of cells to an anti-parallel state.
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