Multi-gate and complementary varactors in FinFET process

US9299699B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Chi-Hsien Lin · Taichung, TW
• Ying-Ta Lu · Hsinchu, TW
• Hsien-Yuan Liao · Hsinchu, TW
• Ho-Hsiang Chen · Hsinchu, TW
• Chewn-Pu Jou · Hsinchu, TW
• Fu-Lung Hsueh

Key dates

• Filing date: Mar 13, 2013
• Grant date: Mar 29, 2016
• Expiry date: May 25, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853

Abstract

A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor.