Field effect transistors including asymmetrical silicide structures and related devices
US9299711B2 · kind B2 · utility
2Cited by
10References
23Claims
0Family size
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Key dates
| Filing date | Sep 20, 2013 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Mar 5, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fin Field Effect Transistor (finFET) can include a source region and a drain region of the finFET. A gate of the finFET can cross over a fin of the finFET between the source and drain regions. First and second silicide layers can be on the source and drain regions respectively. The first and second silicide layers can include respective first and second surfaces that face the gate crossing over the fin, where the first and second surfaces are different sizes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.