Method of forming semiconductor device having stressor
US9299812B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 7, 2015 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Jan 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are methods of forming a semiconductor device having an embedded stressor. The method includes forming a fin active area on a substrate. A gate structure configured to cross the fin active area and cover a side surface of the fin active area, and a gate spacer on a sidewall of the gate structure are formed. Preliminary trenches are formed in the fin active area adjacent to both sides of the gate structure using an anisotropic etching process. An etching select area is formed by oxidizing the fin active area exposed to the preliminary trenches. Trenches are formed by removing the etching select area. A stressor is formed in each of the trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.