Memory device and method of manufacturing the same
US9299826B2 · kind B2 · utility
0Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2014 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Mar 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0411
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.