Semiconductor integrated circuit devices including gates having connection lines thereon
US9299827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2014 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Oct 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.