System and method for dictionary-based cache-line level code compression for on-chip memories using gradual bit removal
US9300320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2014 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Jun 27, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/401
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-pass compression iteratively removes combinations of bits from locations in each word of a cache line of an uncompressed data stream. For each combination of removed bits, the remaining bits in the word values of the cache line are analyzed to generate a compression score. A highest compression score triggers the building of a dictionary from the remaining bits in the word values of the cache line. After a dictionary is built, the method may continue iteratively to create subsequent dictionaries from the words that remain uncompressed in the cache line. To decompress a word, a first bit section of the compressed word is used to identify a dictionary that is then queried for bits indexed in a second bit section of the compressed word. The uncompressed word is reconstructed by interleaving the queried bits with the removed combination of bits from a third bit section of the word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.