Server and power chip detecting method
US9304567B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Aug 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power chip detecting device, applied in a server, includes a power chip, a power sequence control module, a base management controller, a GPIO module, and a signal detecting module. The power sequence control module sends an initial power enable signal to the power chip after the server is switched on, and the power sequence control module receives an initial power good signal from the power chip after the power chip receives the initial power enable signal. The signal detecting module sends a time abnormal result to the GPIO module after determining that time difference between sending out of the initial power enable signal and the initial power good signal is less than a reference value. The GPIO module sends the time abnormal result to the base management controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.