Reducing power consumption and wakeup latency in SSD controllers by not resetting flash devices
US9304577B2 · kind B2 · utility
3Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Jun 14, 2013 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Feb 9, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a memory and a controller. The memory processes a plurality of read/write operations. The controller (i) operates in a first power domain to control power savings operations, and (ii) processes the read/write operations in a second power domain. The first power domain is isolated from the second domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.