Memory controller and data management method thereof
US9304905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Jul 14, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a flash memory controller for mapping the logical addresses to the physical addresses of memory including a plurality of blocks, each having a plurality of pages, wherein the memory controller includes a processor. The processor includes hot page decision unit and an address translation unit. The hot page decision unit classifies pages in each block into hot pages and cold pages based on a predetermined criterion. When there is a plurality of the classified hot pages, the address translation unit respectively arranges the classified hot pages in different target blocks.In accordance with this configuration, upon performing a merge operation, hot pages and cold pages are determined, and the hot pages are respectively distributed to empty blocks, so that concentration of an erase operation on a specific physical block may be avoided, thus wear-leveling may be performed more efficiently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.