Memory controller devices, systems and methods for translating memory requests between first and second formats for high reliability memory devices
US9304953B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2012 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | May 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device can include an interface circuit configured to translate memory access requests at a controller interface of the interface circuit into signals at a memory device interface of the interface circuit that is different from the controller interface, the interface circuit including a write buffer memory configured to store a predetermined number of data values received at a write input of the controller interface, and a read buffer memory configured to mirror a predetermined number of data values stored in the write buffer memory; wherein the memory device interface comprises an address output configured to transmit address values, a write data output configured to transmit write data on rising and falling edges of a periodic signal, and a read data input configured to receive read data at the same rate as the write data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.