Method and systems for detecting and isolating hardware timing channels
US9305166B2 · kind B2 · utility
2Cited by
3References
9Claims
0Family size
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Key dates
| Filing date | Mar 7, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Apr 6, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/556
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for detecting a timing channel in a hardware design includes synthesizing the hardware design to gate level. Gate level information flow tracing is applied to the gate level of the hardware design via a simulation to search for tainted flows. If a tainted flow is found, a limited number of traces are selected. An input on the limited number of traces is simulated to determine whether the traces are value preserving with respect to taint inputs, and to determine that a timing flow exists if the traces are value preserving with respect to the taint inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.