Logical memory architecture, in particular for MRAM, PCRAM, or RRAM
US9305607B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 23, 2012 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | May 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture and method are provided for reading and writing, in parallel or in series, an electronic memory component based on a two-dimensional matrix of two-terminal binary memory unit cells built into a crossbar architecture. The component includes a logical column-selector located outside the matrix and activating at least one column, one or more cells of which are subjected to read or write processing. Also provided is a component and method with the reading of the status of the cells by differential detection on from two cells of two different rows, either between a storage column and a constant reference column, or between two rows or two storage columns. A component is also provided in which specific selection structure is exclusively dedicated to read operations, and/or in which complementary cells in two complementary columns connected together are encoded in a single atomic operation by means of a single write current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.