Reconfigurable load-reduced memory buffer
US9305613B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Feb 5, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Apr 17, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In one example, the memory module also includes a registered buffer having an address bus interface, where the switch may selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.