Write assist circuit for write disturbed memory cell
US9305623B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 26, 2013 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Dec 2, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprises a first memory cell, a second memory cell, and a disturb control circuit. The first memory cell has a first port and a second port. The first port is associated with a first write assist circuit. The second port is associated with a second write assist circuit. The second memory cell has a third port and a fourth port. The third port is associated with a third write assist circuit. The fourth port is associated with a fourth write assist circuit. The disturb control circuit is configured to selectively turn on at least one of the first write assist circuit, the second write assist circuit, the third write assist circuit, or the fourth write assist circuit according to whether the first port, the second port, the third port, or the fourth port is determined to be write disturbed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.