Resistive random access memory and method for manufacturing the same
US9305977B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 25, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Dec 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A resistive random access memory including a substrate, a dielectric layer disposed on the substrate and at least one memory cell string is provided. The memory cell string includes memory cells and second vias. The memory cells are vertically and adjacently disposed in the dielectric layer, and each of the memory cells includes a first via, two conductive lines respectively disposed at two sides of the first via and two variable resistance structures respectively disposed between the first via and the conductive lines. In the vertically adjacent two memory cells, the variable resistance structures of the upper memory cell and the variable resistance structures of the lower memory cell are isolated from each other. The second vias are respectively disposed in the dielectric layer under the first vias and connected to the first vias, and the vertically adjacent two first vias are connected by the second via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.