At-rate SERDES clock data recovery with controllable offset
US9306732B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | May 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(−1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.