Scan flip-flop and associated method
US9310435B2 · kind B2 · utility
6Cited by
7References
3Claims
0Family size
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Key dates
| Filing date | Oct 21, 2014 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Oct 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.