Apparatus for switching a plurality of ALUs between tree and cascade configurations
US9311103B2 · kind B2 · utility
2Cited by
2References
19Claims
0Family size
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Key dates
| Filing date | Feb 11, 2013 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Jan 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arrangement of at least two arithmetic logic units carries out an operation defined by a decoded instruction including at least one operand and more than one operation code. The operation codes and at least one operand are received and corresponding executions are performed by the arithmetic logic units on a single clock cycle. The result of the execution from one arithmetic logic unit is used as an operand by a further arithmetic logic unit. The decoding of the instruction is performed in an immediately preceding single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.