Controlling memory access conflict of threads on multi-core processor with set of highest priority processor cores based on a threshold value of issued-instruction efficiency
US9311142B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Aug 8, 2012 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Feb 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-core processor system includes multiple cores and memory accessible from the cores, where a given core is configured to detect among the cores, first cores having a highest execution priority level; identify among the detected first cores, a second core that caused access conflict of the memory; and control a third core that is among the cores, excluding the first cores and the identified second core, the third core being controlled to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.