Adaptive target charge to equalize bit errors across page types
US9311183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2015 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Jan 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods and/or devices are used to adapt a target charge to equalize bit errors across page types for a storage medium, such as flash memory, in a storage system. In one aspect, the method includes performing a sequence of operations, including: (1) determining a first target charge, a second target charge, and a third target charge, the first, second, and third target charges used for controlling first, second, and third charge distributions, respectively, in cells of the storage medium when data is written to the cells, wherein the second charge distribution is between the first charge distribution and the third charge distribution, (2) determining a first error indicator for lower/fast pages of the storage medium, (3) determining a second error indicator for upper/slow pages of the storage medium, and (4) adjusting the second target charge in accordance with the first error indicator and the second error indicator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.