Patent · US Active

Circuit arrangement and method for testing same

US9311203B2 · kind B2 · utility

3Cited by

3References

17Claims

0Family size

Assignee

Intel Deutschland GmbH · DE

Inventors

Lars Melzer · Dresden, DE
Volker Aue · Dortmund, DE

Key dates

Filing date	Aug 6, 2012
Grant date	Apr 12, 2016
Priority date	—
Expiry date	Dec 23, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/267
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The invention relates to a circuit arrangement and to a method for testing same. A circuit arrangement is provided that includes a plurality of functional units which are coupled by at least one streaming data bus. Each of the functional units includes a plurality of hardware modules and a switch matrix. At least one of the streaming data busses is provided with a data width of at least that of the widest hardware module of any of the functional units of the circuit arrangement. The switch matrices are configurable to establish a streaming data path between and through the plurality of functional units which is used as a test link for any of the hardware modules of the circuit arrangement. The invention provides for non-intrusive real-time tracing in SoCs with a minimum of additional hardware resources and at low cost in terms of die size and power consumption.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.