Task based voting for fault-tolerant fail safe computer systems
US9311212B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Aug 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/165
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a first application that writes a first plurality of tasks to a first memory buffer; a second memory buffer that receives a copy of the first plurality of tasks; a second application that writes a second plurality of tasks to a third memory buffer; and a fourth memory buffer that receives a copy of the second plurality of tasks. The system further includes a first comparison module that generates a first voting signal based on a first comparison between a first task and a second task. The system further includes a second comparison module that generates a second voting signal based on a second comparison between the first task and the second task. The system further includes a first central processing unit (CPU) that selectively determines whether to de-assert a module health signal based on the first voting signal and the second voting signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.