Integrated circuit test-port architecture and method and apparatus of test-port generation
US9311444B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 10, 2014 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Jul 16, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for generating RTL code for a test-port interface of an integrated circuit. In an embodiment, a test-port table is provided as input data. A computer automatically parses the test-port table into data structures and analyzes it to determine input, output, local, and output-enable port names. The computer generates address-detect and test-enable logic constructed from combinational functions. The computer generates one-hot multiplexer logic for at least some of the output ports. The one-hot multiplexer logic for each port is generated so as to enable the port to toggle between data signals and test signals. The computer then completes the generation of the RTL code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.