GOA circuit structure
US9311880B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 21, 2014 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Jan 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/043
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A GOA circuit structure comprises multiple twined GOA units cascaded with each other, each said twined GOA unit comprises the (2N−1)-level GOA unit and the 2N-level GOA unit, which has a first pull-down holding circuit, a second pull-down holding circuit, a third pull-down holding circuit, and a fourth pull-down holding circuit connected with the (2N−1)-level gate signal point (Q(2N−1)) and the 2N-level gate signal point (Q(2N)). By inputting the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal to make the four pull-down holding circuits work alternately. The GOA circuit structure makes each portion work for ¼ time and take rest for ¾ time by sharing the pull-down holding circuit, to reduce the TFT stress of the pull-down holding circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.