Interconnection of several levels of a stack of supports for electronic components
US9312169B2 · kind B2 · utility
0Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2014 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Aug 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method for producing a microelectronic device formed from a stack of supports (W) each provided with one or more electronic components (C) and comprising a conductive structure (170, 470) formed from a first blind conductive via (171b, 472) and a second blind conductive via (171a, 473) with a greater height, the first via and the second via being connected together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.