Method of forming a semiconductor substrate including a cooling channel
US9312202B2 · kind B2 · utility
3Cited by
7References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 21, 2015 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Apr 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor substrate for use in an integrated circuit, the semiconductor substrate including a channel defined on a surface of the substrate. The channel includes a first wall, a second wall, and a third wall. The first wall is recessed from the surface. The second wall extends from the surface to the first wall. The third wall extends from the surface to the first wall and faces the second wall across the channel. At least one of the second wall and the third wall includes a plurality of structures projecting into the channel from the second wall or the third wall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.