Integrated circuit package with spatially varied solder resist opening dimension

US9312237B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Tieyu Zheng · Chandler, US
• Sumit Kumar · Bengaluru, IN
• Sridhar Nara · San Jose, US
• Renee D. Garcia · Suwanee, US
• Manohar S. Konchady · Chandler, US
• Suresh Yeruva · Boise, US
• Lynn H. Chen · Gilbert, US
• Tyler N. Osborn · Gilbert, US
• Sairam Agraharam · Chandler, US

Key dates

• Filing date: Dec 23, 2014
• Grant date: Apr 12, 2016
• Expiry date: Dec 23, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3511
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).