Non-volatile memory device
US9312264B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2013 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Oct 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a non-volatile memory device using a memory transistor including an oxide semiconductor, capable of writing with low power consumption, without receiving an influence of deterioration of a selection transistor connected in series to the memory transistor. A memory cell 1 includes a memory transistor Qm, and first and second selection transistors Q1 and Q2. During a writing operation, the memory transistor Qm and the first selection transistor Q1 are set to the ON state, and the second selection transistor Q2 is set to the OFF state. A writing current is flown to a series circuit of the memory transistor Qm and the first selection transistor Q1. The memory transistor Qm is transited from a first state that indicates a transistor characteristic to a second state that indicates an ohmic resistance characteristic. During a reading operation, the first selection transistor Q1 is set to the OFF state, the second selection transistor Q2 is set to the ON state, a voltage is applied to a series circuit of the memory transistor Qm and the second selection transistor Q2, and it is detected whether the memory transistor Qm is in the first state or the second stat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.