Memory structure and preparation method thereof
US9312484B2 · kind B2 · utility
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4Claims
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Key dates
| Filing date | Nov 13, 2015 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Nov 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
Abstract
A memory structure includes a control unit and a memory unit electrically connected to the control unit. The control unit includes a source and a drain; an active layer in contact with a portion of the source and a portion of the drain; a gate layer; and a gate insulation layer disposed between the active layer and the gate layer. The memory unit includes a bottom electrode layer; a top electrode layer; and a resistive switching layer interposed between the bottom electrode layer and the top electrode layer, which the resistive switching layer and the active layer are formed of aluminum zinc tin oxide (AZTO).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.