Systems and methods for a wafer scale atomic clock
US9312869B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Oct 22, 2013 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Apr 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG04F5/14
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems and methods for a wafer scale atomic clock are provided. In at least one embodiment, a wafer scale device comprises a first substrate; a cell layer joined to the first substrate, the cell layer comprising a plurality of hermetically isolated cells, wherein separate measurements are produced for each cell in the plurality of hermetically isolated cells; and a second substrate joined to the cell layer, wherein the first substrate and the second substrate comprise electronics to control the separate measurements, wherein the separate measurements are combined into a single measurement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.