Electrical transceiver for synchronous Ethernet
US9312900B2 · kind B2 · utility
2Cited by
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7Claims
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Key dates
| Filing date | Oct 17, 2014 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Oct 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0673
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Disclosed is an electrical transceiver for synchronous Ethernet, including: a first interface connected with a host; a second interface including a physical layer (PHY) transceiver connected with a serial link; and a processor connected with the first interface and the second interface, wherein the processor includes a timing control unit controlling a transmission signal transmitted to the second interface from the first interface and a reception signal transmitted to the first interface from the second interface to have the same time delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.