Downlink physical layer processing in wireless networks with symbol rate mapping
US9312994B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2013 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Apr 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2601
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A downlink physical layer processing system includes a transport block segmentation processor that receives a transport block and generates segmented blocks from the transport block, an encoder that encodes the segmented blocks and forms encoded blocks, a mapping processor that maps the encoded blocks to symbols corresponding to resource elements to generate mapped symbols for transmission over a transmission medium, and a transmission signal generator that processes the mapped symbols to generate transmission signals for transmission over the transmission medium. The mapping processor maps the encoded blocks to the symbols in response to a control signal generated by the transmission signal generator. The encoder thereby operates in response to timing of data received by the encoder while the mapping processor operates in response to timing of processing of symbols by the transmission signal generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.