Shift register having multiple processing stages
US9317253B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 12, 2012 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Jul 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1595
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a shift register is provided. The LFSR includes a plurality of processing stages coupled in series, each configured to implement N taps of the LFSR. N single-tap circuits are coupled together in series and arranged to implement the last N taps of the LFSR. Each coefficient(s) of a feedback polynomial of the LFSR is implemented by one of the taps of the plurality of processing stages or the N single-tap circuits. A feedback generation circuit is configured to provide, for each of the plurality of processing stages, a respective feedback signal as a function of polynomial coefficients implemented by the processing stage and output from one or more of the N single tap circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.