Method and apparatus for faulty memory utilization
US9317350B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2013 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Apr 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for faulty memory utilization in a memory system includes: obtaining information regarding memory health status of at least one memory page in the memory system; determining an error tolerance of the memory page when the information regarding memory health status indicates that a failure is predicted to occur in an area of the memory system affecting the memory page; initiating a migration of data stored in the memory page when it is determined that the data stored in the memory page is non-error-tolerant; notifying at least one application regarding a predicted operating system failure and/or a predicted application failure when it is determined that data stored in the memory page is non-error-tolerant and cannot be migrated; and notifying at least one application regarding the memory failure predicted to occur when it is determined that data stored in the memory page is error-tolerant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.