Reliable, low latency hardware and software inter-process communication channel for safety critical system
US9317359B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | May 5, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A fault-tolerant failsafe computer system including an inter-processor communication channel includes a transmission control module that encodes a first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet. The system also includes a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet and ii) decodes the first encoded copy and the second encoded copy. The system further includes a de-duplication module that receives a plurality of data packets and communicates at least one unique data packet of the plurality of data packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.