Cache node processing
US9317436B2 · kind B2 · utility
5Cited by
5References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2013 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Dec 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0868
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for cache node processing that includes generating a cache node in response to a request to write data to storage devices. If logical block address (LBA) of the generated cache node is adjacent to LBA of cache nodes of a cache node list, then check if there are cache nodes that are sequential up to a predefined boundary. If there are cache nodes that are sequential up to the predefined boundary, then flush the data of the sequential cache nodes together as a group up to the predefined boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.