Selective restrictions to memory mapped registers using an emulator
US9317452B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2013 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Jun 18, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A virtual machine environment in which a hypervisor provides direct memory mapped access by a virtual guest to a physical memory device. The hypervisor prevents reading from, writing to, or both, any individual register or registers while allowing unrestricted access to other registers, and without raising any abnormal condition in the guest's execution environment. For example, in one embodiment, the hypervisor can apply memory access protection to a memory page containing a restricted register so that a fault condition can be raised. When an instruction is executed, the hypervisor can intercept the fault condition and emulate the faulting guest instruction. When the emulation accesses the restricted address, the hypervisor can selectively decide whether or not to perform the access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.