Memory frame architecture for instruction fetches in simulation
US9317630B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2012 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Nov 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A simulation technique that handles accesses to a frame of instruction memory by inserting a command object between a frame proxy and a memory frame provides improved throughput in simulation environments. The instruction frame, if present, processes the access to the frame. If an instruction frame is not present for the accessed frame, the memory frame handles the request directly. The instruction frame caches fetched and decoded instructions and may be inserted at the first access to a corresponding instruction memory frame. The instruction frame can track write accesses to instruction memory so that changes to the instruction memory can be reflected in the state of the instruction frame. Additional check frames may be chained between the interface and the memory frame to handle breakpoints, instruction memory watches or other access checks on the instruction memory frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.