Wafer level integration of focal plane arrays having a flexible conductive layer to provide an optical aperture for each pixel
US9318517B1 · kind B1 · utility
1Cited by
4References
28Claims
0Family size
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Key dates
| Filing date | May 29, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Aug 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
Abstract
Apparatus, systems, and methods related to focal plane arrays can be used in a variety of applications. In various embodiments, focal plane arrays can be fabricated on a wafer integration level based on arrangement of a flexible conductive layer for photosensitive pixels of the focal plane arrays. Arrangement of a flexible conductive layer allows for a number of architectures of focal plane arrays. Additional apparatus, systems, and methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.