Semiconductor memory device

US9318532B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Chika Tanaka · Yokohama, JP
• Masumi Saitoh · Yokkaichi, JP
• Kensuke Ota · Kawasaki, JP
• Kiwamu Sakuma · Yokkaichi, JP
• Daisuke Matsushita · Fujisawa, JP

Key dates

• Filing date: Dec 18, 2014
• Grant date: Apr 19, 2016
• Expiry date: Dec 18, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8833

Abstract

A semiconductor memory device comprises: a memory cell array comprising first wiring lines, second wiring lines extending crossing the first wiring lines, and memory cells at intersections of the first and second wiring lines, the memory cells being stacked perpendicularly to a substrate, each memory cell comprising a variable resistance element; a first select transistor layer comprising a first select transistor operative to select one of the first wiring lines; a second select transistor layer comprising a second select transistor operative to select one of the second wiring lines; and a peripheral circuit layer on the substrate, the peripheral circuit layer comprising a peripheral circuit that controls a voltage applied to one of the memory cells. The first select transistor layer is provided below the memory cell array perpendicularly to the substrate. The second select transistor layer is provided above the memory cell array perpendicularly to the substrate.