Methods and systems to reduce location-based variations in switching characteristics of 3D ReRAM arrays
US9318533B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Aug 18, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/52
Abstract
Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.