Signal processing block for a receiver in wireless communication
US9318813B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2010 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Feb 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01Q21/28
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A QRD processor for computing input signals in a receiver for wireless communication relies upon a combination of multi-dimensional Givens Rotations, Householder Reflections and conventional two-dimensional (2D) Givens Rotations, for computing the QRD of matrices. The proposed technique integrates the benefits of multi-dimensional annihilation capability of Householder reflections plus the low-complexity nature of the conventional 2D Givens rotations. Such integration increases throughput and reduces the hardware complexity, by first decreasing the number of rotation operations required and then by enabling their parallel execution. A pipelined architecture is presented (290) that uses un-rolled pipelined CORDIC processors (245a to 245d) iteratively to improve throughput and resource utilization, while reducing the gate count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.