Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals
US9319040B2 · kind B2 · utility
2Cited by
3References
6Claims
0Family size
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Key dates
| Filing date | Dec 23, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Dec 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00241
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory. The controller controls a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal. The controller waits required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.